> Obviously, at the time of the 80486, DDR didn’t exist, so SDRAM is a natural fit.
Neither are a fit, SDRAM was a Pentium/K-6 standard (PC66); the DIMMs ran faster than a non-OC'ed 486 bus, which ran at half the clock of the CPU. 486 "natural fit" would be FPM or EDO, if you wanted to be era-correct.
There were probably some off the wall 486 motherboards back then that supported SDR (post-1993...), but those would have been towards the very end of the 486 consumer life cycle. These did exist in the 486 era, where they had the option to run (or had an embedded) 386 using FPM while there was an open 486 socket and the option, but not requirement to run EDO.
Anyway, this is someone's project, so they can do whatever the heck they want.
Author here.
You’re right—EDO or FPM would be correct for the era. But as others have noted, DDR3 is fundamentally different from early 1990s memory, and it simply won’t run at the very low clock speeds of a 486. SDRAM, on the other hand, behaves in a way that’s much more comparable to the memory used back then.
Out of curiosity, how much of the 138K LUTs (as well as other resources like BRAM) are in use here? I wonder if there's much room to add fancy peripherals, or perhaps "growing" the CPU to achieve better IPC.
It currently uses 44% of the LUTs and 59% of the BRAMs (out of 340 × 2 KB blocks). The chip itself is fairly large and inexpensive, though performance leans toward the lower side.
Silly question. Are there any 486-compatible small CPUs that could be embedded into a project instead of using an FPGA? Given that AMD, Intel and others have the ability to make 486-compatible processors currently, I would have thought you could just buy a CPU or SoC to run 486 code.
Define "486-compatible." As far as I know even intel's newest cpus can run 486 era 16-bit stuff in hardware.
But, a plain answer: Via Eden boards. still use north/southbridge architecture, and are from the mid 2000's.
It's just modern Windows/Linux that have discontinued the ability. Or, perhaps you have 16/32 and 32/64 and are unable to do 16bit on 64bit machines- which still boils down to "operating system."
By far the biggest issue though is that even the Via Eden processor is significantly faster than a 486- and lots of software (especially games) from that era used no-op instruction loops for timing and timers. This results in games like The Incredible Machine's level timer running out in half a second or less.
I left it open as to if it was a hardware or OS level item that prevents 16bit. Because I don't know, and don't care to dig that rabbit hole.
Also- DOSBox is an emulator vs VMs are hardware, no? I suspect A VM won't fix the "no-op loop for timing" issue- with modern processors' lowest clock being 600-800Mhz before it gets C6/C7'd, 30 years of IPC improvement, and the possibility of the CPU itself optimizing such loops (I'm unsure for various reasons): I expect the UX of "just limit how many scheduler slices it gets" to be nasty.
There is a branch of Via (?) in china making enhanced 486 system on a chip "586" systems. I'm on mobile so I don't have the name handy but I'm still hopeful these get cheap enough to enter the hobby space more.
It does, yes. But the DDR RAM available on the target board is DDR3 which is actually quite inconvenient for retro projects for a number of reasons.
Quite apart from the increased complexity, the most important difference is that there's a minimum speed as well as a maximum speed for modern DDR RAM, which means there's usually quite a narrow window of achievable clock rates when getting an FPGA to talk to DDR3.
I suspect that's why the author chose to use the DDR for video: It's usually easy to keep plain old SDRAM in lockstep with a soft-CPU, since you can run it at anything between 133MHz (sometimes even more) and walking pace, so there's no need to deal with messy-and-latency-inducing clock domain crossing.
Streaming video data in bursts into a dual-clock FIFO and consuming it on the pixel clock is a much more natural fit.
Indeed! I have a 486 DX4-100 that is my favorite DOOM system. It has an S3 805 VLB card currently, fast enough. Do you have a favorite VLB card for the 486 or DOOM?
The Edison is a modern System On Module about the size of an SD card but about 3x the thickness of one. It's far more capable: dual 64-bit Silvermont Atom cores, Super scalar out of order. And an additional Quark core as a system monitor, running an independent RTOS. There's also 4GB eMMC, 1GB RAM, WiFi, and Bluetooth on the module. Its quite a remarkable curiosity.
Ten years ago, Intel tried to catch up to ARM in tablets and smartphones, but it was already too late, and this entire segment of Intel was cancelled within a year or two.
Those were actually a 486 microarchitecture with some Pentium instructions added. If you look at the documentation for them, it's obvious that they copy-pasted the 486's and search-and-replaced.
Yes, they did have the bug with the lock prefix. IOT people at Microsoft got NT booting on the Quark and we ran into that problem. I wound up writing a small tool to patch out all the lock prefixes.
I believe the F00F bug was patched out pretty quickly in the Pentium's B2 stepping. Nevertheless, some OSs still have mitigations if they detect an affected CPU (e.g. OpenBSD).
It wasn’t even discovered until 1997, so no that wasn’t exactly early in the Pentium lifecycle at all. There were multiple models and millions of devices affected.
I would love to see ancient tech fabbed out on modern processes.
What's the smallest SOC you could design to run DOOM? What power envelope would that consume (exclusing display/speakers/etc.) At that size and (optimized) transistor count, what speeds could we realistically achieve?
What would a massively-multicore (gpu-style with multi-hundreds or more of cores) one of these run like?
Every time I see a project like this, these thoughts run through my head.
> I would love to see ancient tech fabbed out on modern processes.
> What's the smallest SOC you could design to run DOOM?
Depending on your definition of "modern", more than you think has been done. Intel's Quark were basically 486/Pentium hybrids but fabbed on a fairly modern (at the time) process. While Quark is no longer available as a standalone product, a derivative is part of every modern Intel processor in the form of the Intel ME system co-processor, and it's likely that a number of other Intel products (network cards, QAT accelerators, the ARC GPUs, etc) use them as system controllers as well (Quark essentially came into existence as a "formalization" of the multiple "micro-x86" implementations inside Intel being used as embedded controllers for various non-CPU products).
> What would a massively-multicore (gpu-style with multi-hundreds or more of cores) one of these run like?
This is close to what the original Xeon Phi was. Essentially 60-ish Pentium cores, with modern SMT and 512-bit vector units added. It worked ... OK? If the software development story had been better (e.g. actual first-class support in GCC) I think they could have been a much bigger success, but the need for ICC back in the ICC-costs-real-money days and initially very expensive hardware certainly held them back. At times I do miss some of their behavior.
Arguably a number of the RISC-V-based "AI accelerators" on the market are basically new spins on the same idea: a bunch of small cores, plus large vector/tensor units.
That is a cool idea for sure. It's fun to imagine where the original x86 platform ({80,2,3,4}86) would have gone if it hadn't been remade with the Pentium (superscaler).
I'd pay a decent price for a non-emulated 486 on a credit card sized board, or in a cute little case, with useful peripherals. Something like those Aliexpress mini pocket 386 computers, but 486 is significantly more useful for gaming.
Neither are a fit, SDRAM was a Pentium/K-6 standard (PC66); the DIMMs ran faster than a non-OC'ed 486 bus, which ran at half the clock of the CPU. 486 "natural fit" would be FPM or EDO, if you wanted to be era-correct.
There were probably some off the wall 486 motherboards back then that supported SDR (post-1993...), but those would have been towards the very end of the 486 consumer life cycle. These did exist in the 486 era, where they had the option to run (or had an embedded) 386 using FPM while there was an open 486 socket and the option, but not requirement to run EDO.
Anyway, this is someone's project, so they can do whatever the heck they want.
But, a plain answer: Via Eden boards. still use north/southbridge architecture, and are from the mid 2000's.
It's just modern Windows/Linux that have discontinued the ability. Or, perhaps you have 16/32 and 32/64 and are unable to do 16bit on 64bit machines- which still boils down to "operating system."
By far the biggest issue though is that even the Via Eden processor is significantly faster than a 486- and lots of software (especially games) from that era used no-op instruction loops for timing and timers. This results in games like The Incredible Machine's level timer running out in half a second or less.
Linux isn't really relevant given the time frame.
Also- DOSBox is an emulator vs VMs are hardware, no? I suspect A VM won't fix the "no-op loop for timing" issue- with modern processors' lowest clock being 600-800Mhz before it gets C6/C7'd, 30 years of IPC improvement, and the possibility of the CPU itself optimizing such loops (I'm unsure for various reasons): I expect the UX of "just limit how many scheduler slices it gets" to be nasty.
https://retrodreams.ca/
Review - https://www.youtube.com/watch?v=L9UdU89DDvY
They weren't even that bad considering the little power they needed.
https://classic.sipeed.com/tangconsole
https://archive.is/UD0vH
Quite apart from the increased complexity, the most important difference is that there's a minimum speed as well as a maximum speed for modern DDR RAM, which means there's usually quite a narrow window of achievable clock rates when getting an FPGA to talk to DDR3.
I suspect that's why the author chose to use the DDR for video: It's usually easy to keep plain old SDRAM in lockstep with a soft-CPU, since you can run it at anything between 133MHz (sometimes even more) and walking pace, so there's no need to deal with messy-and-latency-inducing clock domain crossing.
Streaming video data in bursts into a dual-clock FIFO and consuming it on the pixel clock is a much more natural fit.
https://github.com/viti95/FastDoom
And just today, I received the Intel Edison dev kit that I'd purchased on eBay.
The Galileo is a Quark X1000 SoC, two P54C cores. In-order, original 32-bit Pentium.
https://en.m.wikipedia.org/wiki/Intel_Galileo
.
The Edison is a modern System On Module about the size of an SD card but about 3x the thickness of one. It's far more capable: dual 64-bit Silvermont Atom cores, Super scalar out of order. And an additional Quark core as a system monitor, running an independent RTOS. There's also 4GB eMMC, 1GB RAM, WiFi, and Bluetooth on the module. Its quite a remarkable curiosity.
Ten years ago, Intel tried to catch up to ARM in tablets and smartphones, but it was already too late, and this entire segment of Intel was cancelled within a year or two.
https://en.m.wikipedia.org/wiki/Intel_Edison
Next up is building more recent Linux images for these via the Yocto Project and the now cancelled Intel Board Support Packages (BSP).
If you like low power tiny systems, there's a strange amount of fun to be had.
1: https://en.wikipedia.org/wiki/Intel_Quark#Segfault_bug
What's the smallest SOC you could design to run DOOM? What power envelope would that consume (exclusing display/speakers/etc.) At that size and (optimized) transistor count, what speeds could we realistically achieve?
What would a massively-multicore (gpu-style with multi-hundreds or more of cores) one of these run like?
Every time I see a project like this, these thoughts run through my head.
> What's the smallest SOC you could design to run DOOM?
Depending on your definition of "modern", more than you think has been done. Intel's Quark were basically 486/Pentium hybrids but fabbed on a fairly modern (at the time) process. While Quark is no longer available as a standalone product, a derivative is part of every modern Intel processor in the form of the Intel ME system co-processor, and it's likely that a number of other Intel products (network cards, QAT accelerators, the ARC GPUs, etc) use them as system controllers as well (Quark essentially came into existence as a "formalization" of the multiple "micro-x86" implementations inside Intel being used as embedded controllers for various non-CPU products).
> What would a massively-multicore (gpu-style with multi-hundreds or more of cores) one of these run like?
This is close to what the original Xeon Phi was. Essentially 60-ish Pentium cores, with modern SMT and 512-bit vector units added. It worked ... OK? If the software development story had been better (e.g. actual first-class support in GCC) I think they could have been a much bigger success, but the need for ICC back in the ICC-costs-real-money days and initially very expensive hardware certainly held them back. At times I do miss some of their behavior.
Arguably a number of the RISC-V-based "AI accelerators" on the market are basically new spins on the same idea: a bunch of small cores, plus large vector/tensor units.