Heat is mostly driven by leakage current and gate capacitance.
The big issue today is leakage currents. They typical account for around 30%-50% of total chip thermal budget, and they get increasingly difficult to control with smaller devices and lower voltages. They're also get worse with increased temperature(!).
The stacked devices here aren't the worst for leakage currents, but they're not fantastic either. Look at the 2nd graph in section 5: You'll see that the current never drops to zero over the range of gate-source voltages (for V_DS=0.7V). The minimum point is the best-case leakage current, and you can see it's well above zero! (The units on the vertical axis of the graph are unknown btw: The label reads as "current drain-source, arbitrary units")
Not an expert but I wondered this too and did some searching. My understanding is the laser cooling isn't expected to be applicable to silicon logic anytime soon. Its applications are more for specialized contexts like cooling quantum sensors, resonators, imagers, etc.
The big barrier remains heat and this 3D stacking (aka CFET) makes heat worse by increasing density. It's possible much of the density gains offered by CFETs will remain unutilized unless other approaches to solve the fundamental heat problem are found, possibly discovering new high-conductivity MDI materials.
The future is to replace the Si base with something else. Silicon Carbide has higher thermal conductivity. Bismuth-based composites provide much higher frequency.
I'm not certain (never did hardware), but I thought the transistor switching cost was one of the bigger sources of energy loss, not internal conductor resistance between transistors?
The shorter connections could lead to faster rise times though, right? I.e. less capacitance or inductance interfering with getting the field gate charged up?
And the main loss with switching transistors is in the intermediate switching states where it has less than its "full" resistance.
You're correct. Dynamic power consumption depends heavily on frequency, but it's definitely more of a limiting factor than static power consumption which as I understand it (I'm also not an expert) is mainly important for things like low power microcontrollers.
> A city provides a useful analogy. When available land becomes scarce, urban planners initially reduce the spacing between buildings and use roads and open spaces more efficiently. Eventually, however, further horizontal expansion becomes impractical. At that point, the solution is to build upward. High-rise buildings create more usable space on the same piece of land by utilizing the vertical dimension.
The big issue today is leakage currents. They typical account for around 30%-50% of total chip thermal budget, and they get increasingly difficult to control with smaller devices and lower voltages. They're also get worse with increased temperature(!).
The stacked devices here aren't the worst for leakage currents, but they're not fantastic either. Look at the 2nd graph in section 5: You'll see that the current never drops to zero over the range of gate-source voltages (for V_DS=0.7V). The minimum point is the best-case leakage current, and you can see it's well above zero! (The units on the vertical axis of the graph are unknown btw: The label reads as "current drain-source, arbitrary units")
https://news.ycombinator.com/item?id=48510375
The big barrier remains heat and this 3D stacking (aka CFET) makes heat worse by increasing density. It's possible much of the density gains offered by CFETs will remain unutilized unless other approaches to solve the fundamental heat problem are found, possibly discovering new high-conductivity MDI materials.
https://semiengineering.com/the-race-to-replace-silicon/
https://www.plantengineering.com/semiconductor-material-that...
Reducing trace length seems to be the way forward for faster/larger circuits. Signal propagation time on-die is becoming an issue.
Things like Huawei's Logic folding, or TSVs, and so on, attack the issue by reducing signal travel time.
This looks like another building block in that direction.
There's also some push at cooling chips from both sides.
And the main loss with switching transistors is in the intermediate switching states where it has less than its "full" resistance.
Really? someone tell that to my city