Back in the day I was writing a liero clone, and came up with a neat scheme for pixel-perfect collisions (probably serendipitously, no claims it's unique). A 64bit integer can be seen as an 8x8 mask. You can pixel shift it up and down by simply bitshift left or right by 8n bits. Pixel shift left and right required more instructions; if I was to write it today I would probably store an additional rotated version instead (as that would then effectively pixel shift left and right with bit shifts).
You then have the terrain chopped up into these 8x8s too, and can then do a collision test with at most 4 of them with the 1 character/entity mask.
As a SIMD noob, one thing that wasn't obvious to me is that SIMD can also speed you up if your mem throughput is underutilized by having the CPU load more data per instruction. It isn't just about compute speedups, which is typically what it's advertised for. Using perf on Linux has been very educational for me to get an intuition for modern CPU performance.
Yeah, and in the blog post he mentions that he had to transform the data to SoA. If he had done that alone, he might already have seen a speedup from better cache utilization.
Also, I see no mention of alignment in the post. I understand x86/AVX2 likes your load/stores to be aligned, even if it technically allows unaligned access.
Unaligned loads/stores aren't super bad; if still within a cacheline, there's zero penalty, and on crossing cachelines it's alike two ops (except page crossing, which is more bad).
So, for 32B loads/stores and 64B cachelines, it's 1.5x more L1 cache ops (as half of the ops will cross a cacheline); perhaps bad if you're L1-cache-throughput-bound, but less so if you're at L2+ as the extra work sits in L1.
I feel like SIMD has been around for decades. Why has it taken this long to catch on? I feel like I have been hearing it a lot through the past few years. It feels like it’s talked about like some programming silver bullet
You then have the terrain chopped up into these 8x8s too, and can then do a collision test with at most 4 of them with the 1 character/entity mask.
Also, I see no mention of alignment in the post. I understand x86/AVX2 likes your load/stores to be aligned, even if it technically allows unaligned access.
So, for 32B loads/stores and 64B cachelines, it's 1.5x more L1 cache ops (as half of the ops will cross a cacheline); perhaps bad if you're L1-cache-throughput-bound, but less so if you're at L2+ as the extra work sits in L1.
Looking at the Wikipedia article - I wonder if it is because SIMD and SIMT are enabled by hardware first
And you’re using languages like Python or Lua and not using a dependency that uses it for you, forget about it.